1. Field of the Invention
This invention relates to an oscillation-stop detecting device for detecting when a clock signal source does not oscillate normally in a semiconductor device using an s clock signal, such as a microcomputer.
2. Description of the Prior Art
FIG. 13 is a circuit diagram showing a structure of an conventional oscillation-stop detecting device disclosed in JP-A 4/171516. For example, this oscillation-stop detecting device can be adapted to a microcomputer. In FIG. 13, numeral 210 indicates a clock signal oscillator including a inverter 216 and a resistor Rf and functioning with an oscillator 219 connected to an input terminal 212 and output terminal 214 so as to output a clock signal 301; 220 indicates an oscillation-stop detecting section outputting a detection signal 302 of low level when the clock signal 301 stops; 230 indicates a CPU receiving the clock signal 301 and an active-high reset signal 303; 240 indicates a reset signal generator generating a reset signal 305 based on a voltage by a resistor and a capacitor which are connected to a reset signal input terminal 242; and 250 indicates a reset signal controlling section generating the reset signal 303 for the CPU 230 based on the reset signal 305 and the detection signal 302 and providing an initializing signal 307 for the oscillation-stop detecting section.
Next, the operation is described referring to a timing chart shown in FIG. 14.
When the power is turned on for a microcomputer circuit, a reset signal generator 240 generates the reset signal 305, which is kept low for a predetermined period (see FIG. 14(a)). In the reset signal controlling section 250, the reset signal 305 is output through a NAND circuit to the CPU 230 as the signal 303, which is kept high for a predetermined period. At the time, clock signal oscillator 210 generates the clock signal 301 and outputs clock signal 301 to the CPU 230. Since the reset signal 305 becomes high after a predetermined period has passed, the reset sinal 303 for the CPU 230 becomes low and the CPU 230 starts.
In case the voltage level Vdd of the power source becomes low and the clock signal 301 keeps at a low level continuously (see FIGS. 14(a) and 14(b)), an input level of a Schmitt trigger buffer becomes high because a P-channel transistor is OFF in the oscillation-stop detecting section 220. Consequently, an input level of a clock terminal of a D flip/flop in the oscillation-stop detecting section 220 becomes high and the detection signal 302 becomes a low (see FIG. 14(d)). Since the detection signal 302 passes through a NAND circuit in the reset signal controlling section 250, the reset signal 303 indicating a high level is output to CPU 230 (see FIG. 14(f)). As a result, the CPU 230 is reset.
In case the voltage level Vdd returns to the normal level and the clock signal 301 is outputted again, a high level appears at a Q-output terminal of a D flip/flop in the reset signal controlling section 250. Consequently, because the initializing signal 307 becomes active (see FIG. 14(e)), the D flip/flop in the oscillation-stop detecting section 220 is reset. As a result, because the level of the reset signal 303 returns to low level, it becomes possible for the CPU 230 to function again.
As described above, in case the oscillation-stop detecting section 220 detects the stopping of the clock signal 301, an active reset signal 303 is provided for the CPU 230 to reset the CPU 230.
Error protection mechanisms of the microcomputer include safe processing by software, a watch-dog timer in the microcomputer, peripheral circuits outside the microcomputer and so forth. Generally, peripheral circuits and other error protection mechanisms are constructed according to a condition when the microcomputer is reset. In other words, if the reset condition of the microcomputer is kept, the peripheral circuits recognizes that the microcomputer drops into an error condition, if the reset condition of the microcomputer is kept. According to the structure shown in FIG. 13, since the CPU 230 enters a reset condition when the clock signal 301 stops, the peripheral circuits can recognize that the microcomputer enters an error condition.
However, it is possible for the oscillation-stop detecting device to detect the stopping of the clock signal 301 only when the level of the clock signal 230 is fixed to a low level caused by lowering of the voltage level Vdd or the like. Actually, the clock signal 301 stops based on various causes, for example disconnection or short-circuiting of the input and output terminals 212 or 214, or extraction of the oscillator 219 from input or output terminal 212 or 214.
As shown in FIG. 15, there is also a structure in which an oscillator device 218 is connected to the input terminal 212 and the microcomputer is provided with the clock signal 301 from the outside. In this case, the clock signal 301 stops based on various causes, for example, disconnection or short-circuiting of the input and output terminals 212 or 214, or damage to the oscillator device 218.
Since the conventional oscillation-stop detecting device is constructed as above, it is difficult to accurately detect the stopping of the clock signal 301 by various causes.